 . You have to register with your institutional email (@studenti
. You have to register with your institutional email (@studenti .uniroma1.it); reservations without such an email will be considered null!
Please, cancel your reservation if you cannot come. If the form is already closed, you can write me an email.
.uniroma1.it); reservations without such an email will be considered null!
Please, cancel your reservation if you cannot come. If the form is already closed, you can write me an email.
 ).
Basic notions on error-correcting codes: parity bit; longitudinal and vertical parity (https://www.geeksforgeeks.org/error-detection-in-computer-networks/
).
Basic notions on error-correcting codes: parity bit; longitudinal and vertical parity (https://www.geeksforgeeks.org/error-detection-in-computer-networks/ );
Haming Code 4-3 (https://www.tutorialspoint.com/digital_circuits/digital_circuits_error_detection_correction_codes.htm
);
Haming Code 4-3 (https://www.tutorialspoint.com/digital_circuits/digital_circuits_error_detection_correction_codes.htm ; [MM] 7.4). 
Slides 7
Exercises, October 15th, 2021
Sum, subtraction and multiplication in floating point.
Exercises on operations on floating point numbers
Class, October, 19th, 2021
Definition of Boolean algebra. Derived properties: involution, idempotency, annihilator, absorption, De Morgan 
([MM] 2.1--2.4; [K] pgg.23--26 || REMARK: in these texts they use a different set of axioms for defining boolean algebra).
Slides 8
Exercises, October 19th, 2021
Exercises on error-correcting codes; a recapitulation exercise on number conversions and operations.
Exercises on Error-correcting Codes
-
Exercise on Numbers (conversions & operations)
Class, October, 22nd, 2021
Boolean variables and expressions. Dual and complementary expressions. Equivalence among expressions. 
([MM] 1.9).
Boolean functions with 1, 2 or more variables; truth tables. Logic gates 
([MM] 2.5, 2.7, 2.8; [K] pgg.17--19, 31).
NAND, NOR and their universality; XOR and XNOR 
([MM] 3.7, 3.9; [K] pgg.19--23, 47-54).
Slides 9
Exercises, October 22nd, 2021
Equivalences among boolean expressions; simplification of expressions through boolean laws. 
Exercises on Boolean algebra
Class, October 26th, 2021
Boolean expressions in canonical SOP form: minterms and disjunctive normal form.
Relations among truth table of a function and its canonical SOP form.
Turning expressions in normal and canonical SOP form. 
POS normal form; maxterms and conjunctive canonical forms. Turning expressions in normal and canonical POS form. 
Relations among truth table of a function and its canonical POS form.
([MM] 2.6; [K] pgg. 32, 33).
Slides 10
Exercises, October 26th, 2021
Exercises on boolean expressions.
Exercises on boolean operators 
Class, October 29th, 2021
Minimizing BEs; Karnaugh's Maps and representation of BFs through them. Procedure for obtaining a minimal SOP and a minimal POS
Non-fully defined functions and don't care symbols.  
([MM] 3.1, 3.2, 3.3, 3.5, 3.6; [K] pgg. 35-44)
Slides 11
Exercises, October 29th, 2021
Exercises on Canonical and normal forms. 
Exercises on SOP/POS forms
Class, November, 2nd, 2021
Definition of combinatorial net; relation between tra combinatorial nets and BEs.
Analysis of a combinatorial net: procedure and examples. 
Synthesis of a combinatorial net: procedure and examples 
([MM] 4.1, 4.2, 4.3, 4.4; [K] pgg. 27--30, 33-35, ).
Slides 12
Exercises, November, 2nd, 2021
Exercises on the minimization of boolean expressions.
Exercises on SOP/POS minimal forms
Class, November 5th, 2021
Remarkable circuits: natural and integer adder, with overflow conditions; complementator and subtractor. Comparator of natural numbers.
([MM] 4.5, 4.8; [K] pgg. 55-60)
Slides 13
Exercises, November 5th, 2021
Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Class, November 9th, 2021
Encoder and schema with OR matrix; decoder and schema with AND matrix.
ROM: definition and use for realizing boolean functions. PLA: definition and use for realizing boolean functions.
Multiplexer and demultiplexer; use of multiplexer to compute boolean functions. 
([MM] 4.9, 4.10, 4.11; [K] pgg. 60-65)
Slides 14
Exercises, November 9th, 2021
More Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Exercises, November 12th, 2021
Exercises on MUX, PLA and ROM. 
Exercises on ROM/PLA/MUX -- 
Recap Exercise on Synthesis
Exercises, November 16th, 2021: Simulated mid term exam. 
During the class, you'll have 1 hour for solving the exercises. Then, I'll give you the correct solution of the exercises and then we shall spend the remaining time to see and correct your solutions. For this reason, I suggest you to take pictures of your solutions (exercise by exercise) and have them ready in .jpg format to be sent by email. I'll then open your solutions while sharing my screen with you and correct them during the meeting, so that all of you can see my corrections and understand your mistakes (to avoid them in future exams). 
Text -- 
Solutions
Class, November 19th, 2021
Introduction to sequential nets: storage and feedback. Temporal diagrams for variables and circuits. Elementary memory circuits: latch SR (behaviour under the s/r signals, characteristic function, excitation function). Flip-Flop D: definition, characteristic and excitation tables. Flip-Flop JK: definition, characteristic and excitation tables. Flip-Flop T: definition, characteristic and excitation tables. Latches D, JK and T through a latch SR. Clock. Synchronous Latch (gated latch): definition and circuit schema; master-slave flip-flop sensible to the clock's descending wave front ([MM] 5.1--5.4; [K] pgg. 67--76).
Slides 16
Class, November 23rd, 2021
Finite state automata with output: the models of Mealy and Moore. Automata Representation through table and through labeled graphs 
(https://www.ics.uci.edu/~irani/f13-6B/FiniteAutomataRosen.pdf
; [MM] 7.4). 
Slides 7
Exercises, October 15th, 2021
Sum, subtraction and multiplication in floating point.
Exercises on operations on floating point numbers
Class, October, 19th, 2021
Definition of Boolean algebra. Derived properties: involution, idempotency, annihilator, absorption, De Morgan 
([MM] 2.1--2.4; [K] pgg.23--26 || REMARK: in these texts they use a different set of axioms for defining boolean algebra).
Slides 8
Exercises, October 19th, 2021
Exercises on error-correcting codes; a recapitulation exercise on number conversions and operations.
Exercises on Error-correcting Codes
-
Exercise on Numbers (conversions & operations)
Class, October, 22nd, 2021
Boolean variables and expressions. Dual and complementary expressions. Equivalence among expressions. 
([MM] 1.9).
Boolean functions with 1, 2 or more variables; truth tables. Logic gates 
([MM] 2.5, 2.7, 2.8; [K] pgg.17--19, 31).
NAND, NOR and their universality; XOR and XNOR 
([MM] 3.7, 3.9; [K] pgg.19--23, 47-54).
Slides 9
Exercises, October 22nd, 2021
Equivalences among boolean expressions; simplification of expressions through boolean laws. 
Exercises on Boolean algebra
Class, October 26th, 2021
Boolean expressions in canonical SOP form: minterms and disjunctive normal form.
Relations among truth table of a function and its canonical SOP form.
Turning expressions in normal and canonical SOP form. 
POS normal form; maxterms and conjunctive canonical forms. Turning expressions in normal and canonical POS form. 
Relations among truth table of a function and its canonical POS form.
([MM] 2.6; [K] pgg. 32, 33).
Slides 10
Exercises, October 26th, 2021
Exercises on boolean expressions.
Exercises on boolean operators 
Class, October 29th, 2021
Minimizing BEs; Karnaugh's Maps and representation of BFs through them. Procedure for obtaining a minimal SOP and a minimal POS
Non-fully defined functions and don't care symbols.  
([MM] 3.1, 3.2, 3.3, 3.5, 3.6; [K] pgg. 35-44)
Slides 11
Exercises, October 29th, 2021
Exercises on Canonical and normal forms. 
Exercises on SOP/POS forms
Class, November, 2nd, 2021
Definition of combinatorial net; relation between tra combinatorial nets and BEs.
Analysis of a combinatorial net: procedure and examples. 
Synthesis of a combinatorial net: procedure and examples 
([MM] 4.1, 4.2, 4.3, 4.4; [K] pgg. 27--30, 33-35, ).
Slides 12
Exercises, November, 2nd, 2021
Exercises on the minimization of boolean expressions.
Exercises on SOP/POS minimal forms
Class, November 5th, 2021
Remarkable circuits: natural and integer adder, with overflow conditions; complementator and subtractor. Comparator of natural numbers.
([MM] 4.5, 4.8; [K] pgg. 55-60)
Slides 13
Exercises, November 5th, 2021
Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Class, November 9th, 2021
Encoder and schema with OR matrix; decoder and schema with AND matrix.
ROM: definition and use for realizing boolean functions. PLA: definition and use for realizing boolean functions.
Multiplexer and demultiplexer; use of multiplexer to compute boolean functions. 
([MM] 4.9, 4.10, 4.11; [K] pgg. 60-65)
Slides 14
Exercises, November 9th, 2021
More Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Exercises, November 12th, 2021
Exercises on MUX, PLA and ROM. 
Exercises on ROM/PLA/MUX -- 
Recap Exercise on Synthesis
Exercises, November 16th, 2021: Simulated mid term exam. 
During the class, you'll have 1 hour for solving the exercises. Then, I'll give you the correct solution of the exercises and then we shall spend the remaining time to see and correct your solutions. For this reason, I suggest you to take pictures of your solutions (exercise by exercise) and have them ready in .jpg format to be sent by email. I'll then open your solutions while sharing my screen with you and correct them during the meeting, so that all of you can see my corrections and understand your mistakes (to avoid them in future exams). 
Text -- 
Solutions
Class, November 19th, 2021
Introduction to sequential nets: storage and feedback. Temporal diagrams for variables and circuits. Elementary memory circuits: latch SR (behaviour under the s/r signals, characteristic function, excitation function). Flip-Flop D: definition, characteristic and excitation tables. Flip-Flop JK: definition, characteristic and excitation tables. Flip-Flop T: definition, characteristic and excitation tables. Latches D, JK and T through a latch SR. Clock. Synchronous Latch (gated latch): definition and circuit schema; master-slave flip-flop sensible to the clock's descending wave front ([MM] 5.1--5.4; [K] pgg. 67--76).
Slides 16
Class, November 23rd, 2021
Finite state automata with output: the models of Mealy and Moore. Automata Representation through table and through labeled graphs 
(https://www.ics.uci.edu/~irani/f13-6B/FiniteAutomataRosen.pdf ).
Automata equivalence. From Mealy to Moore and vice versa 
(https://lms.uop.edu.jo/moodle/pluginfile.php/6059/mod_resource/content/0/chap08.pdf
).
Automata equivalence. From Mealy to Moore and vice versa 
(https://lms.uop.edu.jo/moodle/pluginfile.php/6059/mod_resource/content/0/chap08.pdf )
Slides 17
-
Slides 18
Class, November 26th, 2021
State equivalence in an automaton: minimization algorithm through triangolar table 
([MM] 5.7; http://www.informatik.uni-bremen.de/agbs/lehre/ss05/pi2/hintergrund/minimize_dfa.pdf
)
Slides 17
-
Slides 18
Class, November 26th, 2021
State equivalence in an automaton: minimization algorithm through triangolar table 
([MM] 5.7; http://www.informatik.uni-bremen.de/agbs/lehre/ss05/pi2/hintergrund/minimize_dfa.pdf )
Slides 19
Exercises, November 26th, 2021
Exercises on automata design. 
Exercises on automata design
Class, November 30th, 2021
Analysis of sequential nets: future states table; state diagram of the corresponding automaton; verbal description 
([MM] 5.5; [K] 77-83).
Slides 20
Exercises, November 30th, 2021
Exercises on the traduction Mealy/Moore and Moore/Mealy;
Exercises on automata minimization.
Exercises on model traduction
-
Exercises on the minimization
Class, December 3rd, 2021
Synthesis of a sequential net: from the verbal description to the automaton, minimization, future states table, excitation functions for the FFs, circuital schema 
([MM] 5.8; [K] 83--88).
Slides 21
Exercises, December 3rd, 2021
Exercises on the analysis of synchronous sequential nets. 
Exercises on sequential analysis
Class, December 7th, 2021
Memory registers: all possible combinations of parallel and sequential load and unload.
Shifters: right, left, bidirectional; with bit holding; circular 
([MM] 6.1, 6.2; [K] pgg. 89--92).
Slides 23
Exercises, December 7th, 2021
Examples of sequential synthesis.
Slides 22
Class, December 10th, 2021
Synthesis of the upwise counter modulo 8; upwise counters modulo 2^n.
Downwise counter modulo 2^n. Bidirectional counters (http://www.allaboutcircuits.com/vol_4/chpt_11/3.html
)
Slides 19
Exercises, November 26th, 2021
Exercises on automata design. 
Exercises on automata design
Class, November 30th, 2021
Analysis of sequential nets: future states table; state diagram of the corresponding automaton; verbal description 
([MM] 5.5; [K] 77-83).
Slides 20
Exercises, November 30th, 2021
Exercises on the traduction Mealy/Moore and Moore/Mealy;
Exercises on automata minimization.
Exercises on model traduction
-
Exercises on the minimization
Class, December 3rd, 2021
Synthesis of a sequential net: from the verbal description to the automaton, minimization, future states table, excitation functions for the FFs, circuital schema 
([MM] 5.8; [K] 83--88).
Slides 21
Exercises, December 3rd, 2021
Exercises on the analysis of synchronous sequential nets. 
Exercises on sequential analysis
Class, December 7th, 2021
Memory registers: all possible combinations of parallel and sequential load and unload.
Shifters: right, left, bidirectional; with bit holding; circular 
([MM] 6.1, 6.2; [K] pgg. 89--92).
Slides 23
Exercises, December 7th, 2021
Examples of sequential synthesis.
Slides 22
Class, December 10th, 2021
Synthesis of the upwise counter modulo 8; upwise counters modulo 2^n.
Downwise counter modulo 2^n. Bidirectional counters (http://www.allaboutcircuits.com/vol_4/chpt_11/3.html ).
Counter modulo k, with k different from 2^n. Counter of 1s on an input line.
([MM] 6.3, 6.4, 6.5; [K] pgg. 93--98).
Asynchronous counters (http://www.allaboutcircuits.com/vol_4/chpt_11/2.html
).
Counter modulo k, with k different from 2^n. Counter of 1s on an input line.
([MM] 6.3, 6.4, 6.5; [K] pgg. 93--98).
Asynchronous counters (http://www.allaboutcircuits.com/vol_4/chpt_11/2.html ).
FF with asynchronous inputs (PRE)SET and CLEAR (http://www.allaboutcircuits.com/vol_4/chpt_10/7.html
).
FF with asynchronous inputs (PRE)SET and CLEAR (http://www.allaboutcircuits.com/vol_4/chpt_10/7.html ). 
Counters modulo k with k different from 2**n, using asynchronous CLEARs of the FFs (http://highered.mcgraw-hill.com/sites/dl/free/0072823151/56549/vra23151_ch07.pdf
). 
Counters modulo k with k different from 2**n, using asynchronous CLEARs of the FFs (http://highered.mcgraw-hill.com/sites/dl/free/0072823151/56549/vra23151_ch07.pdf , sez. 7.10). 
Presettable counters (http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#load
, sez. 7.10). 
Presettable counters (http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#load ).
Slides 24
Exercises, December 10th, 2021
Exercises on the synthesis of sequential nets.
Exercises on sequential synthesis
Class, December 14th, 2021
Register Interconnection: 4 modalities. Fixed source and destination (point-to-point, with logic gates and tristate buffers); variable source and fixed destination  (with MUX); fixed source and variable destination (with DEC); variable source and destination (mesh, both with source and destination registers different and coinciding; bus). Design examples and a simplified schema of the ALU (notes).
Slides 25
-
Slides 26
Exercises, December 14th, 2021
Exercise of sequential synthesis using a counter.
Exercises, December 17th, 2021
Exercises on Interconnections.
Interconnection exercises
Exercises, December 21st, 2021: Simulated second mid term and oral exam. 
During the first 1 hour of the online meeting, you'll have to solve a few exercises on the second part of the course; then, I'll give you the correct solution of the exercises and discuss you solutions. In the second part, some of your colleagues will undergo a normal oral exam, so that you can understand the kind of questions I'm about to ask you and how to answer them. 
Text
-
Solutions
).
Slides 24
Exercises, December 10th, 2021
Exercises on the synthesis of sequential nets.
Exercises on sequential synthesis
Class, December 14th, 2021
Register Interconnection: 4 modalities. Fixed source and destination (point-to-point, with logic gates and tristate buffers); variable source and fixed destination  (with MUX); fixed source and variable destination (with DEC); variable source and destination (mesh, both with source and destination registers different and coinciding; bus). Design examples and a simplified schema of the ALU (notes).
Slides 25
-
Slides 26
Exercises, December 14th, 2021
Exercise of sequential synthesis using a counter.
Exercises, December 17th, 2021
Exercises on Interconnections.
Interconnection exercises
Exercises, December 21st, 2021: Simulated second mid term and oral exam. 
During the first 1 hour of the online meeting, you'll have to solve a few exercises on the second part of the course; then, I'll give you the correct solution of the exercises and discuss you solutions. In the second part, some of your colleagues will undergo a normal oral exam, so that you can understand the kind of questions I'm about to ask you and how to answer them. 
Text
-
Solutions
 ACSAI/CA1/AA2021 Web
 ACSAI/CA1/AA2021 Web
 Create New Topic
 Create New Topic
 Index
 Index
 Search
 Search
 Changes
 Changes
 Notifications
 Notifications
 RSS Feed
 RSS Feed
 Statistics
 Statistics
 Preferences
 Preferences
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
           
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
|  |  |  
      Questo sito usa cookies, usandolo ne accettate la presenza. (CookiePolicy)
       Torna al Dipartimento di Informatica   |  |  |  | 
 
  Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.