phone: 064991 8434
office: Viale Regina Elena 295  Palazzina E  2nd Floor, room 205
email: gorla@diNOSPAM.uniroma1.it (delete NOSPAM)
Moreover, Sapienza imposes that students that cannot attend the exam in presence can also attend it remotely (but in this case, you must provide a major force reason for this option and provide me evidence by email). The remote exam will be a quick test (5 questions in 5 minutes with multiple choice answers), and only those who provide a correct answer on 4 over 5 of these questions will be admitted to the oral exam, that will be 1 hour long (with both theoretical questions and practical exercises).
Please, cancel your reservation if you cannot come. If the form is already closed, you can write me an email.
The overall program of the course is the following:
[MM] M. Morris Mano, M. D. Ciletti: Digital design, 4th edition. Pearson/Prentice Hall.
[K] A. F. Kana: Digital Logic Design. (Available online)
The exam is made up by a written part and an oral one.
Rules for the written exam:
Date and time of every written exam are timely published in the Bachelor Degree webpage, under the "Exams" tab.
The oral exam must be done just after the written exam (usually, the week after). The exact dates for the oral exams are communicated together with the results of the written exam a few days after the written exam. REMARK: a fully negative oral exam can also lead to cancel the written exam (that has to be done again).
Here you can find all topics, classbyclass, together with slides and references on the text books
Class, September 28th, 2021 Overall introduction to the course. Historical evolution of computers. Representation of information, definition of code and its requirements; Definition and properties of positional numeric systems, the binary code. Changing base for natural numbers: from base 10 to base b, from base b to base 10; representation interval in base b with a fixed number of digits; octal and hexadecimal systems ([MM] 1.1, 1.2, 1.3, 1.4; [K] pgg. 15).
Exercises, October 1st, 2021 Converting natural numbers from base 10 to binary, octal, hexadecimal and other bases, and vice versa.
Class, October 1st, 2021 Arithmetic operations on naturals.
Class, October 5th, 2021 Representing integers in two’s complement: representation interval, how to find the opposite of a given number. Sum and subtraction in two’s complement ([MM] 1.5, 1.6; [K] pgg. 69).
Exercises, October 5th, 2021 Operations on naturals in bases different from 10.
Exercises on operations among naturals
Class, October 7th, 2021 Converting rational numbers in fixed point: from binary to decimal, and vice versa ([MM] 1.3). Floating point representation: representation intervals and Standard IEEE ([K] pgg. 1012).
Exercises, October 7th, 2021 Operations on integers.
Class, October 12th, 2021 Operations in floating point representation.
Exercises, October 12th, 2021 Fixed and floating point representation of rationals.
Class, October 15th, 2021 ASCII Code ([MM] 1.7, [K] pg. 1416) and UNICODE ( wikipedia page). Basic notions on errorcorrecting codes: parity bit; longitudinal and vertical parity (https://www.geeksforgeeks.org/errordetectionincomputernetworks/); Haming Code 43 (https://www.tutorialspoint.com/digital_circuits/digital_circuits_error_detection_correction_codes.htm; [MM] 7.4).
Exercises, October 15th, 2021 Sum, subtraction and multiplication in floating point.
Exercises on operations on floating point numbers
Class, October, 19th, 2021 Definition of Boolean algebra. Derived properties: involution, idempotency, annihilator, absorption, De Morgan ([MM] 2.12.4; [K] pgg.2326  REMARK: in these texts they use a different set of axioms for defining boolean algebra).
Exercises, October 19th, 2021 Exercises on errorcorrecting codes; a recapitulation exercise on number conversions and operations.
Exercises on Errorcorrecting Codes  Exercise on Numbers (conversions & operations)
Class, October, 22nd, 2021 Boolean variables and expressions. Dual and complementary expressions. Equivalence among expressions. ([MM] 1.9). Boolean functions with 1, 2 or more variables; truth tables. Logic gates ([MM] 2.5, 2.7, 2.8; [K] pgg.1719, 31). NAND, NOR and their universality; XOR and XNOR ([MM] 3.7, 3.9; [K] pgg.1923, 4754).
Exercises, October 22nd, 2021 Equivalences among boolean expressions; simplification of expressions through boolean laws.
Class, October 26th, 2021 Boolean expressions in canonical SOP form: minterms and disjunctive normal form. Relations among truth table of a function and its canonical SOP form. Turning expressions in normal and canonical SOP form. POS normal form; maxterms and conjunctive canonical forms. Turning expressions in normal and canonical POS form. Relations among truth table of a function and its canonical POS form. ([MM] 2.6; [K] pgg. 32, 33).
Exercises, October 26th, 2021 Exercises on boolean expressions.
Exercises on boolean operators
Class, October 29th, 2021 Minimizing BEs; Karnaugh's Maps and representation of BFs through them. Procedure for obtaining a minimal SOP and a minimal POS Nonfully defined functions and don't care symbols. ([MM] 3.1, 3.2, 3.3, 3.5, 3.6; [K] pgg. 3544)
Exercises, October 29th, 2021 Exercises on Canonical and normal forms.
Class, November, 2nd, 2021 Definition of combinatorial net; relation between tra combinatorial nets and BEs. Analysis of a combinatorial net: procedure and examples. Synthesis of a combinatorial net: procedure and examples ([MM] 4.1, 4.2, 4.3, 4.4; [K] pgg. 2730, 3335, ).
Exercises, November, 2nd, 2021 Exercises on the minimization of boolean expressions.
Exercises on SOP/POS minimal forms
Class, November 5th, 2021 Remarkable circuits: natural and integer adder, with overflow conditions; complementator and subtractor. Comparator of natural numbers. ([MM] 4.5, 4.8; [K] pgg. 5560)
Exercises, November 5th, 2021 Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Class, November 9th, 2021 Encoder and schema with OR matrix; decoder and schema with AND matrix. ROM: definition and use for realizing boolean functions. PLA: definition and use for realizing boolean functions. Multiplexer and demultiplexer; use of multiplexer to compute boolean functions. ([MM] 4.9, 4.10, 4.11; [K] pgg. 6065)
Exercises, November 9th, 2021 More Exercises on the analysis and synthesis of combinatorial nets.
Exercises on analysis and synthesis of combinatorial nets
Exercises, November 12th, 2021 Exercises on MUX, PLA and ROM.
Exercises on ROM/PLA/MUX  Recap Exercise on Synthesis
Exercises, November 16th, 2021: Simulated mid term exam. During the class, you'll have 1 hour for solving the exercises. Then, I'll give you the correct solution of the exercises and then we shall spend the remaining time to see and correct your solutions. For this reason, I suggest you to take pictures of your solutions (exercise by exercise) and have them ready in .jpg format to be sent by email. I'll then open your solutions while sharing my screen with you and correct them during the meeting, so that all of you can see my corrections and understand your mistakes (to avoid them in future exams).
Class, November 19th, 2021 Introduction to sequential nets: storage and feedback. Temporal diagrams for variables and circuits. Elementary memory circuits: latch SR (behaviour under the s/r signals, characteristic function, excitation function). FlipFlop D: definition, characteristic and excitation tables. FlipFlop JK: definition, characteristic and excitation tables. FlipFlop T: definition, characteristic and excitation tables. Latches D, JK and T through a latch SR. Clock. Synchronous Latch (gated latch): definition and circuit schema; masterslave flipflop sensible to the clock's descending wave front ([MM] 5.15.4; [K] pgg. 6776).
Class, November 23rd, 2021 Finite state automata with output: the models of Mealy and Moore. Automata Representation through table and through labeled graphs (https://www.ics.uci.edu/~irani/f136B/FiniteAutomataRosen.pdf). Automata equivalence. From Mealy to Moore and vice versa (https://lms.uop.edu.jo/moodle/pluginfile.php/6059/mod_resource/content/0/chap08.pdf)
Class, November 26th, 2021 State equivalence in an automaton: minimization algorithm through triangolar table ([MM] 5.7; http://www.informatik.unibremen.de/agbs/lehre/ss05/pi2/hintergrund/minimize_dfa.pdf)
Exercises, November 26th, 2021 Exercises on automata design.
Class, November 30th, 2021 Analysis of sequential nets: future states table; state diagram of the corresponding automaton; verbal description ([MM] 5.5; [K] 7783).
Exercises, November 30th, 2021 Exercises on the traduction Mealy/Moore and Moore/Mealy; Exercises on automata minimization.
Exercises on model traduction  Exercises on the minimization
Class, December 3rd, 2021 Synthesis of a sequential net: from the verbal description to the automaton, minimization, future states table, excitation functions for the FFs, circuital schema ([MM] 5.8; [K] 8388).
Exercises, December 3rd, 2021 Exercises on the analysis of synchronous sequential nets.
Exercises on sequential analysis
Class, December 7th, 2021 Memory registers: all possible combinations of parallel and sequential load and unload. Shifters: right, left, bidirectional; with bit holding; circular ([MM] 6.1, 6.2; [K] pgg. 8992).
Exercises, December 7th, 2021 Examples of sequential synthesis.
Class, December 10th, 2021 Synthesis of the upwise counter modulo 8; upwise counters modulo 2^n. Downwise counter modulo 2^n. Bidirectional counters (http://www.allaboutcircuits.com/vol_4/chpt_11/3.html). Counter modulo k, with k different from 2^n. Counter of 1s on an input line. ([MM] 6.3, 6.4, 6.5; [K] pgg. 9398). Asynchronous counters (http://www.allaboutcircuits.com/vol_4/chpt_11/2.html). FF with asynchronous inputs (PRE)SET and CLEAR (http://www.allaboutcircuits.com/vol_4/chpt_10/7.html). Counters modulo k with k different from 2**n, using asynchronous CLEARs of the FFs (http://highered.mcgrawhill.com/sites/dl/free/0072823151/56549/vra23151_ch07.pdf, sez. 7.10). Presettable counters (http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#load).
Exercises, December 10th, 2021 Exercises on the synthesis of sequential nets.
Exercises on sequential synthesis
Class, December 14th, 2021 Register Interconnection: 4 modalities. Fixed source and destination (pointtopoint, with logic gates and tristate buffers); variable source and fixed destination (with MUX); fixed source and variable destination (with DEC); variable source and destination (mesh, both with source and destination registers different and coinciding; bus). Design examples and a simplified schema of the ALU (notes).
Exercises, December 14th, 2021 Exercise of sequential synthesis using a counter.
Exercises, December 17th, 2021 Exercises on Interconnections.
Exercises, December 21st, 2021: Simulated second mid term and oral exam. During the first 1 hour of the online meeting, you'll have to solve a few exercises on the second part of the course; then, I'll give you the correct solution of the exercises and discuss you solutions. In the second part, some of your colleagues will undergo a normal oral exam, so that you can understand the kind of questions I'm about to ask you and how to answer them.
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