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<!-- ---+!! %MAKETEXT{"Welcome to the [_1] web" args="<nop>%WEB%"}% --> <table width=100% bgcolor="#CC0000" cellpadding="20"> <tr><td align="center" bgcolor="#CC0000"> </td></tr> <tr><td align="left" bgcolor="#FFFFFF"> <font color="#CC0000" , size=+2><b>Advanced Parallel Architecture - Architetture avanzate e parallele</b></font> <br> <br> <font size=+1><a href="http://twiki.di.uniroma1.it/twiki/view/Users/AnnalisaMassini"><font color="#505050">Annalisa Massini</font></a></font> <br> <br> <font color="#505050"> *Office Hours*: appointment by email </font> </td></tr> <tr><td align="left" bgcolor="#F7F7F7"><font color="#CC0000" size=+1><b>News</b></font><br> <br> <font color="#505050"> * *Grades of July 5th test are below*. * *Paper presentation:* * Paper for oral presentation can be chosen by students, but *must be approved* by the teacher. Please, *send a copy of proposed papers to the teacher for approval*. * Students are required to present the selected paper using *slides*, in *20-30 minutes*. <!-- * *Winter tests* will be: * *January 17th, 10:00 a.m.*, Aula Alfa * *February 2nd, 10:00 a.m.*, Aula Alfa * Students are required: * *to register on Infostud* and * *to select the part of the written exam* they intend to take (Part A, Part B or both), on page [[http://twiki.di.uniroma1.it/twiki/view/Prenotazioni/2018_01_17_TestAdvancedParallelArchitectures][January test]] or [[http://twiki.di.uniroma1.it/twiki/view/Prenotazioni/2018_02_02_TestAdvancedParallelArchitectures][February test]] * *Remember* that: * You *may use your calculator* * *Cell phones are not allowed* during the exam. * *The presentation of papers is scheduled for 11 October at 10:00 am in Seminari room, via Salaria 113, III floor.* * *Students wishing to give the presentation on October 11 must send an email to the professor.* * *Paper presentation:* * Paper for oral presentation *must be approved* by the teacher. Please, *send a copy of proposed papers to the teacher for approval*. * Students are required to present the selected paper using *slides*, in *20-30 minutes*. * Alternatively to the paper presentation, student can present the result of a project, whose topic and goal is approved by the teacher. * *Grades of September 20th test are below*. * *September test* will be: * *September 20th, 10:00 a.m.*, Aula Seminari, via Salaria, 3rd floor. * *Students are required to select the part of the written exam they intend to take (Part A, Part B or both), on page* http://twiki.di.uniroma1.it/twiki/view/Prenotazioni/2017_09_20_AdvancedParallelArchitectures * *Remember* that you may use your calculator, and that *cell phones are not allowed* during the exam. * *Paper presentation will be 26th, July 2017, 10:00 a.m., Aula Seminari, via Salaria, 3rd floor.* * Students can present the selected paper using *slides*, in *20-30 minutes*. * Please, *send a copy of proposed papers to the teacher for approval*. * *Students are required to register on the* [[http://twiki.di.uniroma1.it/twiki/view/Prenotazioni/2017_07_26_AdvancedParallelArchitectures][26th July exam (paper presentation) registration page]]. * *Grades of 5th July test are below*. * Students can examine their tests on *July 18th, 2:00 p.m., Teacher's room*. * Note that: * You *may use your calculator* * *Cell phones are not allowed* during the exam. * *Complete test* will be: * *June 13th* 2:30 p.m. Aula Alfa * *July 5th* 10 a.m., Aula Alfa * *Complete test will consist of two parts*, covering topics of midterm and end-of-term tests respectively. * Student can take one part only of the complete test, if they succeded in the partial test or prefer to split the test. End-of-term exam will be Thursday 1st, June, 10 a.m., Aula Alfa. Students that didn't take the midterm test are allowed to attend the end-of-term test. *Midterm exam will be held during class time on Thursday, April 20 at 12:00, in Room Alfa.* Students *are required to register* for the exam on Infostud. <br> Please note that *registration is open until April 18*. *Cancellation* Due to illness, thursday 6th April's lecture *is cancelled*. *Classes will regularly start on February 21st, 2017.* *Lecture on April 11th, will be at 10:00, in Room Alfa, and will cover exercises for the midterm exam.* * Il prossimo scritto si terrà il *13 luglio alle ore 10* in Sala Runioni, Via Salaria III piano. La lezione del *21 maggio* è posticipata al *22 maggio* alle ore 14 in Aula Alfa. La lezione potrebbe protrarsi (al più fino alle 16) in modo da poter completare l'argomento (Cache Coherence). La prova intermedia si terrà il 14 aprile alle ore 10 in aula Alfa.* Argomenti della prova intermedia: * esercizi su pipeline delle istruzioni, pipeline delle operazioni aritmetiche, sistemi di numerazione ridondanti * domande a risposta aperta su argomenti illustrati a lezione. * La lezione di giovedì *5 marzo* è cancellata per impegno istituzionale. * Martedì *3 marzo* ci sarà *doppia lezione*: lezione di recupero *dalle 10:15 alle 11:45*, lezione regolare *dalle 14:30 alle 16*. *Cancellation* Tuesday 29th April's lecture *is cancelled* due to illness. <tr><td align="left" bgcolor="#FFFFF0"><font color="#FF8C00" size=+1><b>Avviso - News</b></font><br> <br> <font color="#3F467A"> *Homeworks* Students may hand in their homeworks in Colossus Laboratory: *Reminder: there is no lesson on Tuesday 18th March* --> <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Aim of the course - Scopo del corso </b></font><br> <font color="#505050"> The aim of this course is to acquire an understanding and appreciation of a computer system and to learn to harness parallelism to sustain performance improvements, starting from the knowledge of Computer Architecture derived from undergraduate courses. The course presents: the classification of parallel architectures of the Flynn’s Taxonomy and a classification for architectures in the MIMD class; interconnection networks and features of different communication requests; protocols for cache coherence; metrics and measurements of performance, and performance optimization. A deep knowledge of the computer architecture, a careful use of different forms of parallelism and the performance analysis sustain the design of parallel algorithms and the study strategies for problem decomposition. --- Lo scopo del corso è quello di acquisire la capacità di comprensione e di valutazione di una particolare architettura e di saper sfruttare diversi tipi di parallelismo, allo scopo di incrementare le prestazioni in maniera adeguata, partendo dalle conoscenze acquisite nei corsi di Architettura degli Elaboratori della laurea triennale. Nel corso, verrà descritta la classificazione delle architetture parallele secondo Flynn, e una classificazione per la classe MIMD. Si introdurranno le reti di interconnessione e i problemi legati ai diversi tipi di comunicazione. Si descriveranno i diversi protocolli per Cache Coherence. Si parlerà infine di prestazioni (metriche, misure e ottimizzazione) L’utilità del corso nasce dal fatto che una conoscenza approfondita dell’architettura, un attento uso del parallelismo e l’analisi delle prestazioni sono aspetti che dovrebbero sempre affiancare il progetto di algoritmi paralleli e lo studio di strategie di decomposizione di problemi e di distribuzione di carico. </td></tr></font> </td></tr> <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Syllabus - Programma di massima del corso </b></font><br> <font color="#505050"> * Von Neumann's Architecture limitations. * Instruction pipeline and arithmetic operations pipeline. Vector processors. Dataflow architecture. Multicore and multithreading. * Parallel Architectures. Flynn’s Taxonomy and other classifications. Forms of parallelism. SIMD and MIMD architectures. * Interconnection topologies and interconnection networks. Routing Functions. Static Networks. Dynamic Networks. Combining Networks. * Cache Coherence: Snooping Protocols and Directory-based Protocols. Memory Consistency. Message Passing Systems. * Manycore Architectures: GPU (and CUDA). * Performance metrics and measurement Amdahl's Law. Performance optimization: work distribution and load balance, locality, communication. --- * Limiti dell'architettura di Von Neumann. * Pipeline delle istruzioni e delle operazioni. Macchine vettoriali. Macchine data-flow. Multicore e multithreading. * Architetture parallele. Classificazione di Flynn e altre classificazioni. Tipi di parallelismo. Multiprocessori (SIMD e MIMD). * Topologie e reti di interconnessione. Funzioni di routing. Reti statiche, reti dinamiche, reti combinate. * Protocolli per Cache Coherence: Snooping e Directory-based. Memory Consistency. Message Passing Systems. * Architetture manycore: GPU (cenni su CUDA). * Prestazioni: metriche e misure. Legge di Amdahl. Ottimizzazione di prestazioni: distribuzione del carico, località, comunicazioni. <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Lectures </b></font><br> <font color="#505050"> Lectures will be held on *Tuesday* and *Thursday*, 12:00-14:00 in Aula Alfa. ----- *Lecture 1 - February 21st, 2017* Introduction to the course. Motivations to Parallel Architectures. Application Trends. Technology Trends. (Culler, Singh - Ch. 1) [[%ATTACHURL%/2017-lesson1-Introduction.pdf][Lecture 1 - Introduction (part 1)]] <br> *Lecture 2 - February 23rd, 2017* Architectural Trends: Bit Level Parallelism, Instruction Level Parallelism, Thread Level Parallelism. Flynn's Taxonomy. Considerations on performance: Speed-up and Communication cost. (Culler, Singh, Gupta - Ch. 1) [[%ATTACHURL%/2017-lesson2-Introduction.pdf][Lecture 2 - Introduction (part 2)]] <br> *Lecture 3 - February 28th, 2017* Summary on computer architecture. Von Neumann's architecture.Instruction execution, Instruction Set, Instruction format. Addressing modes. Hardwired and microprogrammed CU. [[%ATTACHURL%/2017-lesson3-ArchVonNeumann.pdf][Lecture 3 - Computer architecture and organization (part 1)]] <br> *Lecture 4 - March 2nd, 2017* Summary on computer architecture. Modules and connections. Bus. Memory Hierarchy. Cache Memory. [[%ATTACHURL%/2017-lesson4-ArchVonNeumann.pdf][Lecture 4 - Computer architecture and organization (part 2)]]<br> __Lecture March 7th, 2017__ _Cancelled_ <br> *Lecture 5 - March 9th, 2017* Main memory. I/O modules. ([[%ATTACHURL%/2017-lesson4bis-ArchVonNeumann.pdf][Computer architecture and organization (part 3)]]). Instruction pipelining (Hennessy, Patterson - Appendix C, Sections C1, C2 - [[%ATTACHURL%/2017-lesson5-Pipelinepart1.pdf][Lecture 5 - Pipeline (part 1)]]) <br> *Lecture 6 - March 14th, 2017* Pipeline hazards. Exercises. [[%ATTACHURL%/2017-lesson56-Pipeline.pdf][Lecture 6 - Pipeline (part 1 + part 2)]]<br> *Lecture 7 - March 16th, 2017* Arithmetic operations. Pipeline of arithmetic operations. [[%ATTACHURL%/2017-lesson7-Computer-arithmetic.pdf][Lecture 7 - Computer arithmetic]]<br> *Lecture 8 - March 21st, 2017* Redundant number representations for carry-free addition. Modified Signed Digit (MSB) and Redundant Binary. [[%ATTACHURL%/2017-lesson8-Redundant-representations.pdf][Lecture 8 - Redundant number representations]]<br> *Lecture 9 - March 23rd, 2017* Residue number system. Circuit evaluation: delay and area. [[%ATTACHURL%/2017-lesson9-Residue-representations-circuit.pdf][Lecture 9 - Residue representation and circuit evaluation]]<br> *Lecture 10 - March 28th, 2017* State of art in Bioinformatics and Project Proposals - Tiziana Castrignanò - CINECA [[%ATTACHURL%/Castrignan-Projects2017.pdf][Castrignanò - Project Proposals 2017]] <br> *Lecture 11 - March 30th, 2017* Data dependences and name dependences. Loop-carried dependences. (Hennessy, Patterson - Chapter 3, Sect. 3.1 and Chapter 4, Sect. 4.5) [[%ATTACHURL%/2017-lesson11-LoopLevelParallelism.pdf][Lecture 11 - Instruction level parallelism and Loop-carried dependences]]<br> __Lecture April 4th, 2017__ _Cancelled (Big Data midterm exam)_ <br> __Lecture April 6th, 2017__ _Cancelled due to illness_ <br> *Lecture 12 - April 11th, 2017* Exercises on Circuit propagation time and area; residue number systems; RB representation; instruction pipelining; true dependences, output dependences, antidependences, loop carried dependences; pipelined operations. [[%ATTACHURL%/2017-lesson12-Exercises.pdf][Lecture 12 - Exercises]] - [[%ATTACHURL%/1994-redundantAO.pdf][RB representation]] <br> __Lecture 13 - April 20th, 2017__ [[%ATTACHURL%/Esonero20apr17.pdf][Midterm 20 april 2017]]<br> *Lecture 14 - April 27th, 2017* Classifications of parallel architectures. Interconnection networks. [[%ATTACHURL%/2017-lesson14-Multiproc-InterconnectionNetworks.pdf][Lecture 14 - Parallel architectures - Interconnection Networks]]<br> *Lecture 15 - May 2nd, 2017* Evaluation of interconnection networks. Multistage interconnection networks. Clos networks. Benes Network. Equivalence of logN stage MIN. Equivalence classes for (2logN-1) stage MIN. [[%ATTACHURL%/2017-lesson15-InterconnectionNetworks.pdf][Lecture 15 - Interconnection Networks]] [[%ATTACHURL%/2017-lesson15-EquivalenceJPDC-2004.pdf][Equivalence classes paper]] <br> *Lecture 16 - May 4th, 2017* Exercises on interconnection networks. <br> *Lecture 17 - May 9th, 2017* Vector Architecture. Description and scheme of CRAY-1 Vector Architecture optimizations. [[%ATTACHURL%/2017-lesson17-VectorArchitecture.pdf][Lecture 17 - Vector Architectures]] (Hennessy, Patterson - Chapter 4, Sect. 4.2) <br> *Lecture 18 - May 11th, 2017* Graphics Processing Units. [[%ATTACHURL%/2017-lesson18-GPU.pdf][Lecture 18 - GPUs]] (Hennessy, Patterson - Chapter 4, Sect. 4.2- Kirk, Hwu - Chapter 3, 4, 5; Barlas - Chapter 6) <br> *Lecture 19 - May 16th, 2017* Exercises on GPU (Kirk, Hwu - Chapter 3, 4). [[%ATTACHURL%/EserciziGPU.pdf][Exercises on GPU]]<br> *Lecture 20 - May 18th, 2017* Cache Coherence in Shared Memory Systems [[%ATTACHURL%/2017-lesson20-CoherenceSharedMemory-HP.pdf][Lecture 20 - Cache Coherence]] (Hennessy, Patterson - Chapter 5, Sect. 5.2 and 5.4) Slide 1-43<br> *Lecture 21 - May 23th, 2017* Cache Coherence in Shared Memory Systems [[%ATTACHURL%/2017-lesson20-CoherenceSharedMemory-HP.pdf][Lecture 20 - Cache Coherence]] (Hennessy, Patterson - Chapter 5, Sect. 5.2 and 5.4) Slide 44-60 Exercises on Snooping protocol. [[%ATTACHURL%/2017-lesson21-CacheCoherence-Exercises.pdf][Lecture 21 - Cache Coherence Exercises]]<br> *Lecture 22 - May 25th, 2017* Amdhal Law and Performance Equation (Hennessy, Patterson - Chapter 1, Sect. 1.9)<br> [[%ATTACHURL%/2017-lesson22-Performance-Amdhal.pdf][Lecture 22 - Amdhal Law and Performance Equation]]<br> <!-- *Lecture 23 - June 1st, 2017* End-of-term exam --> ---- <font color="#CC0000" size=+1 ><b>Past year lectures </b></font><br> * [[LecturesAY2015][Lectures 2014/2015]] <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Textbooks - Testi di riferimento </b></font><br> <font color="#505050"> * Parallel Computer Architecture: A Hardware/Software Approach, David E. *Culler*, Jaswinder P. *Singh* and Anoop *Gupta*, Morgan Kaufmann, 1998 * Computer Architecture, Fifth Edition: A Quantitative Approach, John L. *Hennessy*, David A. *Patterson*, Morgan Kaufmann, 2011 * Programming Massively Parallel Processors: A Hands-on Approach, David B. *Kirk*, Wen-mei W. *Hwu*, Morgan Kaufmann, 2010 * Multicore and GPU Programming An Integrated Approach, Gerassimos *Barlas*, Morgan Kaufmann, 2014 <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Exam - Esame </b></font><br> <font color="#505050"> * Students attending the lessons can take a mid-term exam and a final exam (or a whole exam). Mid-term and final exam (or whole exam) consist in a written test and exercises. * Project or oral exam. ----- *Text of exams* * Exams 2016/2017 * [[%ATTACHURL%/Esame13giu2017-partA.pdf][Exam - June 13rd, 2017 - part A]] * [[%ATTACHURL%/Esame13giu2017-partB.pdf][Exam - June 13rd, 2017 - part B]] * [[%ATTACHURL%/Esonero1giu2017.pdf][End-of-term - June 1st, 2017]] * [[%ATTACHURL%/Esonero20apr17.pdf][Midterm - April 20th, 2017]]<br> * Exams 2014/2015 * [[%ATTACHURL%/Esame13lug2015.pdf][Exam - July 15th, 2015]] * [[%ATTACHURL%/Esame26giu2015.pdf][Exam - June 26th, 2015]] * [[%ATTACHURL%/Esonero11giu2015.pdf][Final exam - June 11th, 2015]] * [[%ATTACHURL%/Esonero14apr15.pdf][Midterm exam - April 14th, 2015]]<br> ----- *Grades* * [[%ATTACHURL%/Grade-5jul2018.pdf][Grade July 5th 2018]] * [[%ATTACHURL%/Grade-2feb2018.pdf][Grade February 2nd 2018]] * [[%ATTACHURL%/Grade-20sept2017.pdf][Grade September 20th 2017]] * [[%ATTACHURL%/Grade-5julyl2017.pdf][Grade July 5th, 2017]] * [[%ATTACHURL%/Grade-13junel2017.pdf][Grade June 13rd, 2017]] * [[%ATTACHURL%/Grade-1junel2017.pdf][Grade end-of-term test (June 1st, 2017)]] * [[%ATTACHURL%/Grade-20april2017.pdf][Grade Midterm Exam (April 20th, 2017)]] <!-- * [[%ATTACHURL%/VotiEsame13lug2015.pdf][Results Exam - July 15th, 2015]] * [[%ATTACHURL%/VotiEsame26giu2015.pdf][Results Exam - June 26th, 2015]] * [[%ATTACHURL%/VotiEsonero11giu2015.pdf][Results Final Exam (June 11th 2015)]] * [[%ATTACHURL%/VotiEsonero14apr2015.pdf][Results Midterm Exam (April 14th 2015)]] --> </font> </td></tr> <tr><td align="center" bgcolor="#CC0000"> </td></tr> </table> -- Users.AnnalisaMassini <!-- ---++ %MAKETEXT{"Available Information"}% * ... * ... * ... ---++ <nop>%WEB% Web Utilities <form action='%SCRIPTURLPATH{"search"}%/%WEB%/'> * <input type="text" name="search" size="22" /> <input type="submit" class="twikiSubmit" value="%MAKETEXT{"Search"}%" /> - [[WebSearchAdvanced][%MAKETEXT{"advanced search"}%]] * WebTopicList - all topics in alphabetical order * WebChanges - recent topic changes in this web * WebNotify - subscribe to an e-mail alert sent when topics change * WebRss, WebAtom - RSS and ATOM news feeds of topic changes * WebStatistics - listing popular topics and top contributors * WebPreferences - preferences of this web </form> -->
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