<br /> <tr><td align="left" bgcolor="#FFFFFF" ><font color="#CC0000" size=+1><b>Lectures 2014-2015 </b></font><br> <font color="#505050"> *Lecture hours:* Tuesday and Thursday 14:30-16:00 - Aula Alfa. <br /><br /> *Lecture February 24th, 2015* Introduction to the course. Motivations to Parallel Architectures. Application Trends. Technology Trends. (Culler, Singh - Ch. 1) [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson1-Introduction.pdf][2015-lesson1-Introduction]] <br /> __Lecture February 26th, 2015__ _Cancelled_ <br /> *Lecture March 3rd, 2015* Architectural Trends: Bit Level Parallelism, Instruction Level Parallelism, Thread Level Parallelism. Flynn's Taxonomy. Considerations on performance: Speed-up and Communication cost. (Culler, Singh, Gupta - Ch. 1) [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson2-Introduction.pdf][2015-lesson2-Introduction]] <br /> *Lecture March 3rd, 2015* Summary on computer architecture. Von Neumann's architecture. Description of CPU, hardwired and microprogrammed CU. Instruction execution, Instruction Set, Instruction format. Addressing modes. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson3-ArchVonNeumann.pdf][2015-lesson3-ComputerArchitecture]] <br /> *Lecture March 10th, 2015* Summary on computer architecture. Modules and connections. Bus. Memory Hierarchy. Cache Memory. Main Memory. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015_lesson4-ArchVonNeumann.pdf][2015-lesson4-ComputerArchitecture]] <br /> *Lecture March 12th, 2015* I/O modules (see [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015_lesson4-ArchVonNeumann.pdf][2015-lesson4-ComputerArchitecture]]). Instruction pipelining: description; hazards. (Hennessy, Patterson - Appendix C, Sections C1, C2) <br /> *Lecture March 17th, 2015* Arithmetic operations. Pipeline of arithmetic operations. <br /> *Lecture March 19th, 2015* Redundant number representations for carry-free addition: RB and MSB. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/Articoli-RedundantNumbers.pdf][Suggested papers to read]] <br /> *Lecture March 24th, 2015* Exercises. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/molt-pipe-ca2.pdf][2'complement pipelined multiplier scheme]] <br /> *Lecture March 26th, 2015* Classifications of parallel architectures. Interconnection networks. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson-Multiproc-InterconnectionNetworks.pdf][Multiprocessors and Interconnection Networks]] <br /> *Lecture March 31st, 2015* Evaluation of interconnection networks: node degree, diameter, scalability, routing algorithm. Multistage interconnection networks: Butterfly, Baseline, Omega; Banyan property. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/MIN.pdf][Images of MINs]] <br /> __April 14th, 2015__ [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/Esonero14apr15.pdf][Midterm exam]] <br /> *Lecture April 21st, 2015* Summary on interconnection networks. Equivalence of logN stage MIN. Benes Network. <br /> *Lecture April 23th, 2015* Equivalence classes for (2logN-1) stage MIN. Vector Architecture. Decription and scheme of CRAY-1 <br /> *Lecture April 28th, 2015* Vector Architecture optimizations. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson-VectorArchitecture.pdf][Vector Architecture]] (Hennessy, Patterson - Chapter 4, Sect. 4.2) <br /> *Lecture April 30th, 2015* Exercises on interconnection networks. <br /> __Lecture May 5th, 2015__ _Cancelled_ <br /> *Lecture May 7th, 2015* Graphics Processing Units. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson-GPU.pdf][GPU]] (Hennessy, Patterson - Chapter 4, Sect. 4.4) <br /> *Lecture May 12th, 2015* Graphics Processing Units, part 2. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson-GPU2.pdf][GPU Part 2]] (Kirk, Hwu - Chapter 3, 4, 5; Barlas - Chapter 6 <br /> *Lecture May 14th, 2015* Exercises on GPU (Kirk, Hwu - Chapter 3, 4). Loop data dependences and name dependences. (Hennessy, Patterson - Chapter 4, Sect. 4.5) <br /> *Lecture May 19th, 2015* Detailed Loop data dependences and name dependences. Data-Flow Machine. <br /> *Lecture May 21st, 2015* Cache Coherence in Shared Memory Systems [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/lesson-SharedMemory-HP.pdf][Cache Coherence]] (Hennessy, Patterson - Chapter 5, Sect. 5.2 and 5.4) <br /> *Lecture May 26th, 2015* Amdhal Law and Performance Equation [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/2015-lesson20-Performance-Amdhal.pdf][Amdhal & Performance]] (Hennessy, Patterson - Chapter 1, Sect. 1.9) <br /> *Lecture May 28th, 2015* Exercises. [[http://twiki.di.uniroma1.it/pub/AAP/WebHome/EsercisesAmdhalPerformance.pdf][Esercises on Amdhal Law and Performance Equation]] <br /><br /> -- %USERSIG{AnnalisaMassini - 2017-02-24}%
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